EDN

Statistical Static Timing Analysis – A Better Alternative

Traditionally static timing analysis (STA) is used to verify if a CMOS digital design can meet the target speed at various process and interconnect corners. In practice, the worst-case slow or ...
Embedded

Static timing analysis: bridging the gap between simulation and silicon

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...
EDN

Overcoming Static Timing Issues in Low-Power 3G Chips

The power issues encountered by today's mobile phone manufacturers is well documented. With cameras, web browsers, and other processing-intensive tasks entering next-generation phones, designers try ...
Electronic Design

Improve Logic Timing with Worst-Case Analysis

Worst-case circuit analysis (WCCA) is a cost-effective means of screening a design to verify with a high degree of confidence that potential defects and deficiencies are identified and eliminated ...